The 555 timer is a single integrated circuit that realises the bistable, monostable, and astable multivibrators with a fixed internal voltage reference. A resistive divider sets two thresholds at $\tfrac{1}{3}V_{CC}$ and $\tfrac{2}{3}V_{CC}$, two comparators detect when external nodes cross those thresholds, an SR latch stores the resulting state, and an open-collector transistor sinks an external timing capacitor on demand. The mode of operation is selected by what is wired to the timing pins.
The 555 owes its name to the three nominally-equal 5 k$\Omega$ resistors that form an internal divider between $V_{CC}$ and ground. The divider taps fix two reference voltages,
An upper comparator compares the THRES pin against $V_{TH}$, and a lower comparator compares the TRIG pin against $V_{TL}$. The two comparator outputs drive the R and S inputs of an internal SR latch, whose Q output is buffered to the OUT pin. The complementary output $\overline{Q}$ drives the base of an NPN discharge transistor whose collector is exposed at the DISCH pin; this transistor grounds DISCH whenever the latch is in the reset state.
Both thresholds are fixed fractions of $V_{CC}$, so the timing of every configuration is independent of supply voltage. A 555 powered at 5 V and at 12 V produces the same period for the same external $R$ and $C$.
In astable mode the 555 produces a continuous square wave with no external trigger. The capacitor charges from $\tfrac{1}{3}V_{CC}$ to $\tfrac{2}{3}V_{CC}$ through the series combination $R_1 + R_2$, then discharges from $\tfrac{2}{3}V_{CC}$ back to $\tfrac{1}{3}V_{CC}$ through $R_2$ alone, with the discharge transistor providing the path to ground.
Solving $v_C(t) = V_{CC} + (v_C(0) - V_{CC})\,e^{-t/\tau}$ for the time taken to traverse the band gives
The total period and frequency are
The duty cycle, defined as the fraction of the period for which OUT is high, is
This expression is always greater than $\tfrac{1}{2}$, so the standard astable cannot produce a 50% duty cycle. A 50% duty cycle is achieved either by placing a small-signal diode across $R_2$ (so the charging path bypasses $R_2$ and uses $R_1$ alone), or by using a CMOS variant of the 555 with separate charge and discharge resistors.
In monostable mode the 555 emits a single fixed-width pulse on each negative trigger. At rest the discharge transistor is on, the capacitor is held near 0 V, the output sits low, and the chip waits indefinitely. A brief negative pulse on TRIG (pin 2) drives the lower comparator output high and sets the latch. The output snaps high, the discharge transistor releases the capacitor, and $v_C$ rises along an exponential through $R$ toward $V_{CC}$.
The pulse ends when $v_C$ reaches $\tfrac{2}{3}V_{CC}$, at which point the upper comparator resets the latch. Solving $v_C(t) = V_{CC}(1 - e^{-t/RC}) = \tfrac{2}{3}V_{CC}$ gives
As with the astable, the pulse width is independent of $V_{CC}$ because the threshold scales with the supply. The standard 555 monostable is non-retriggerable: a second trigger pulse arriving during the output-high state is ignored. Retriggerable behaviour requires either a CMOS retriggerable variant or an external reset network.
In bistable mode no timing capacitor is used. THRES (pin 6) is tied to ground so the upper comparator can never fire, and DISCH (pin 7) is left disconnected. With the upper comparator inactive, the internal SR latch is exposed directly through the active-low TRIG input (which sets the latch) and the active-low RESET input (which clears it).
The output is now a pure latched signal. A brief negative pulse on TRIG drives OUT to $V_{CC}$ and the circuit holds that state indefinitely. A brief negative pulse on RESET drives OUT back to 0 and the circuit again holds. In the absence of either pulse the output retains its last value; this is one bit of stored state.
The idealised circuits above are accurate for the chip's logical behaviour but omit several practical details that matter in a working board. The notes below cover the most important ones.
CTRL exposes the $\tfrac{2}{3}V_{CC}$ tap externally. Driving CTRL from an audio source modulates both thresholds proportionally, which produces frequency modulation in astable mode and pulse-width modulation in monostable mode. When CTRL is not used, it should be bypassed to ground through a 10 nF capacitor so supply noise does not couple into the threshold.
The bipolar NE555 sources and sinks up to roughly 200 mA on the OUT pin, so it can drive a small speaker, an LED with a series resistor, or a relay coil directly. The CMOS variants (TLC555, ICM7555) drive less current but operate to a lower $V_{CC}$ and switch faster.
The output stage and the discharge transistor produce large $\Delta i / \Delta t$ on the supply. A local 100 nF ceramic capacitor across $V_{CC}$ to ground, placed close to the chip, is essential to prevent supply spikes from coupling into the timing network. The CTRL bypass capacitor handles the divider node separately.
The bipolar NE555 is reliable up to about 500 kHz in astable mode; above this, comparator propagation delay and switching transients dominate the measured period. CMOS variants reach a few MHz. Long-period timing is bounded by capacitor leakage and comparator input bias current, which both shorten the effective time constant for very large $RC$.
The standard astable cannot reach 50% duty because the charging path uses $R_1 + R_2$ while the discharging path uses only $R_2$. A small-signal diode placed across $R_2$ (anode at the discharge node, cathode at the threshold node) lets the capacitor charge through $R_1$ alone, giving $D = R_1 / (R_1 + R_2)$ and access to duty cycles below 50%.
Stimulus pulse trains for nerve and muscle stimulators (astable rate generator paired with a monostable pulse-width shaper); PWM motor and LED drivers; capacitive- and resistive-sensing oscillators; switch-debounce one-shots; missing-pulse and watchdog timers; tone generators for alarms and audible feedback.